add Makefile's comment
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Makefile
50
Makefile
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@ -1,34 +1,50 @@
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# VARIABLES
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CXX = g++
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SRC_DIR = src
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OBJ_DIR = .obj
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INC_DIR = inc
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WFLAGS = -Wall
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OFLAG = -o
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TARGET = main
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EXEC = ./$(TARGET)
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INCLUDE = -I $(INC_DIR)
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# [--------------------DIRECTORIES--------------------]
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# SRC_DIR is the source directory
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# OBJ_DIR is the object directory
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# INC_DIR is the header directory
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SRC_DIR := src
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OBJ_DIR := obj
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INC_DIR := inc
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# [--------------------COMPILE & RUN--------------------]
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# CXX is the keyword to compile .cpp src files
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# WFLAG is a flag to detect all the warnings
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# OFLAG is the flag to rename the output of the compiler
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# TARGET is the name of the output
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# INCLUDE add to g++ path the custom include path
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CXX := g++
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WFLAGS := -Wall
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OFLAG := -o
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TARGET := main
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INCLUDE := -I $(INC_DIR)
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# FUNCTION:
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SRCS := $(shell find $(SRC_DIR) -name "*.cpp") # extract all file in src/
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FILES := $(notdir $(basename $(SRCS))) # extract the name of the file
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OBJS := $(addprefix $(OBJ_DIR)/,$(addsuffix .o,$(FILES))) # concat obj/ + FILES + .o
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# [--------------------FUNCTION--------------------]
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# SRCS extract all file in src/
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# FILES extract the name of the file
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# OBJS concat obj/ + FILES + .o
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SRCS := $(shell find $(SRC_DIR) -name "*.cpp")
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FILES := $(notdir $(basename $(SRCS)))
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OBJS := $(addprefix $(OBJ_DIR)/,$(addsuffix .o,$(FILES)))
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all: execute
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execute: linking
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@ echo execute...
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@ $(EXEC)
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@ ./$(TARGET)
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@ echo ...terminate
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linking: $(OBJS)
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@ echo linking
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@ $(CXX) $(WFLAGS) $(OFLAG) $(TARGET) $(OBJS)
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$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp
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$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp $(OBJ_DIR)
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@ echo compile $<
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@ $(CXX) $(WFLAGS) -c $< $(OFLAG) $@ $(INCLUDE)
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$(OBJ_DIR):
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mkdir -p $(OBJ_DIR)
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clean:
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@ -rm -f $(OBJS)
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@ rm -rf $(OBJ)
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