199 lines
4.4 KiB
ArmAsm
199 lines
4.4 KiB
ArmAsm
;;
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;; enableA20.s (adapted from Visopsys OS-loader)
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;;
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;; Copyright (c) 2000, J. Andrew McLaughlin
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;; You're free to use this code in any manner you like, as long as this
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;; notice is included (and you give credit where it is due), and as long
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;; as you understand and accept that it comes with NO WARRANTY OF ANY KIND.
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;; Contact me at jamesamc@yahoo.com about any bugs or problems.
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;;
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enableA20:
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;; This subroutine will enable the A20 address line in the keyboard
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;; controller. Takes no arguments. Returns 0 in eax on success,
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;; -1 on failure. Written for use in 16-bit code, see lines marked
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;; with 32-BIT for use in 32-bit code.
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pusha
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;; Make sure interrupts are disabled
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cli
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;; Keep a counter so that we can make up to 5 attempts to turn
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;; on A20 if necessary
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mov cx, 5
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.startAttempt1:
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;; Wait for the controller to be ready for a command
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.commandWait1:
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xor ax, ax
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in al, 0x64
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bt ax, 1
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jc .commandWait1
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;; Tell the controller we want to read the current status.
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;; Send the command 0xD0: read output port.
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mov al, 0xD0
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out 0x64, al
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;; Wait for the controller to be ready with a byte of data
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.dataWait1:
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xor ax, ax
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in al, 0x64
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bt ax, 0
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jnc .dataWait1
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;; Read the current port status from port 0x60
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xor ax, ax
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in al, 0x60
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;; Save the current value of (E)ax
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;; push ax ; 16-BIT
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push eax ; 32-BIT
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;; Wait for the controller to be ready for a command
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.commandWait2:
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in al, 0x64
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bt ax, 1
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jc .commandWait2
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;; Tell the controller we want to write the status byte again
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mov al, 0D1h
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out 0x64, al
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;; Wait for the controller to be ready for the data
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.commandWait3:
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xor ax, ax
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in al, 0x64
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bt ax, 1
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jc .commandWait3
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;; Write the new value to port 0x60. Remember we saved the old
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;; value on the stack
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;;pop ax ; 16-BIT
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pop eax ; 32-BIT
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;; Turn on the A20 enable bit
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or al, 0b00000010
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out 0x60, al
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;; Finally, we will attempt to read back the A20 status
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;; to ensure it was enabled.
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;; Wait for the controller to be ready for a command
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.commandWait4:
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xor ax, ax
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in al, 0x64
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bt ax, 1
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jc .commandWait4
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;; Send the command 0xD0: read output port.
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mov al, 0xD0
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out 0x64, al
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;; Wait for the controller to be ready with a byte of data
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.dataWait2:
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xor ax, ax
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in al, 0x64
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bt ax, 0
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jnc .dataWait2
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;; Read the current port status from port 0x60
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xor ax, ax
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in al, 0x60
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;; Is A20 enabled?
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bt ax, 1
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;; Check the result. If carry is on, A20 is on.
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jc .success
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;; Should we retry the operation? If the counter value in Ecx
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;; has not reached zero, we will retry
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loop .startAttempt1
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;; Well, our initial attempt to set A20 has failed. Now we will
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;; try a backup method (which is supposedly not supported on many
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;; chipsets, but which seems to be the only method that works on
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;; other chipsets).
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;; Keep a counter so that we can make up to 5 attempts to turn
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;; on A20 if necessary
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mov cx, 5
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.startAttempt2:
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;; Wait for the keyboard to be ready for another command
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.commandWait6:
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xor ax, ax
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in al, 0x64
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bt ax, 1
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jc .commandWait6
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;; Tell the controller we want to turn on A20
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mov al, 0xDF
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out 0x64, al
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;; Again, we will attempt to read back the A20 status
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;; to ensure it was enabled.
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;; Wait for the controller to be ready for a command
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.commandWait7:
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xor ax, ax
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in al, 0x64
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bt ax, 1
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jc .commandWait7
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;; Send the command 0xD0: read output port.
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mov al, 0xD0
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out 0x64, al
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;; Wait for the controller to be ready with a byte of data
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.dataWait3:
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xor ax, ax
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in al, 0x64
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bt ax, 0
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jnc .dataWait3
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;; Read the current port status from port 0x60
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xor ax, ax
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in al, 0x60
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;; Is A20 enabled?
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bt ax, 1
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;; Check the result. If carry is on, A20 is on, but we might warn
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;; that we had to use this alternate method
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jc .warn
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;; Should we retry the operation? If the counter value in Ecx
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;; has not reached zero, we will retry
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loop .startAttempt2
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;; OK, we weren't able to set the A20 address line. Do you want
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;; to put an error message here?
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jmp .fail
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.warn:
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;; Here you may or may not want to print a warning message about
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;; the fact that we had to use the nonstandard alternate enabling
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;; method
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.success:
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;sti ; Note: When this is uncommented, shit breaks. Probably because the CPU
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; throws a fault or a trap without the IDT being loaded, so it triple
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; faults and resets. Or maybe not, who knows
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popa
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xor eax, eax
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ret
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.fail:
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; sti
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popa
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mov eax, -1
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ret
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