30 lines
393 B
Makefile
30 lines
393 B
Makefile
CC := gcc
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SRC := src
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OBJ := obj
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TARGET := a.out
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SRCS := $(shell find $(SRC) -name *.c)
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FILES := $(notdir $(basename $(SRCS)))
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OBJS := $(addprefix $(OBJ)/,$(addsuffix .o,$(FILES)))
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FLAGS := -Werror -Wall
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all: clear build
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build: $(OBJS)
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$(CC) $(FLAGS) $(OBJS)
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./$(TARGET)
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$(OBJ)/%.o: $(SRC)/%.c
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$(CC) -Werror -Wall -c $< -o $@
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only: build
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clean: clear
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-rm -f $(OBJS)
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clear:
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clear
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